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義隆單片機EM78 的開發指令集
來源： 日期：2021-9-9
EM78系列是義隆電子公司所推出的八位元微控制器，此IC是采用先進的CMOS技術制造，因此具有低功率消耗、高執行速度的特性。其內含看門狗計時器、可程式計數器、低功率消耗模式及雙向三態I/O等強大功
| 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | Mnemonic | C? | Z? | Deion |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | opcode | Miscellaneous instructions | ||||||||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | NOP* | No operation (MOVW 0,W) | ||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | DAA† | C | ||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CONTW* | Write CONT register (CONT ← W) | ||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | SLEEP* | Go into standby mode (WDT ← 0, stop clock) | ||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CLRWDT* | Restart watchdog timer (WDT ← 0) | ||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | f | IOW f* | Copy W to I/O control register (f = 5–7, 11–15) | |||||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | ENI† | Enable interrupts | ||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | DISI† | Disable interrupts | ||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | RET | Return from subroutine, W unmodified | ||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | RETI | Return from interrupt; return & enable interrupts | ||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | CONTR† | Read CONT register (W ← CONT) | ||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | f | IOR f† | Copy I/O control register to W (f = 5–7, 11–15) | |||||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | TBL† | C | Z | PCL += W. preserve PC bits 8 & 9 |
| 0 | 0 | opcode | d | register | ALU operations same as 12- and 14-bit PIC | |||||||||||
| 0 | 1 | op | bit | register | Bit operations same as 12- and 14-bit PIC | |||||||||||
| 1 | 0 | op | k | Control transfers same as 14-bit PIC | ||||||||||||
| 1 | 1 | opcode | 8-bit immediate | Operations with W and 8-bit literal: W ← OP(k,W) | ||||||||||||
| 1 | 1 | 0 | op | k | MOV/IOR/AND/XOR, same as 12-bit PIC | |||||||||||
| 1 | 1 | 1 | 0 | 0 | k | RETLW k | W ← k, then return from subroutine | |||||||||
| 1 | 1 | 1 | 0 | 1 | k | SUBLW k | C | Z | W ← k−W (W ← k+~W+1) | |||||||
| 1 | 1 | 1 | 1 | 0 | k | INT k† | Push PC, PC ← k (software interrupt, usually k=1) | |||||||||
| 1 | 1 | 1 | 1 | 1 | k | ADDLW k | C | Z | W ← k+W | |||||||
| 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | Mnemonic | C? | Z | Deion |
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